MediaTek Dimensity 9500 SoC Tipped to Offer Improved Ray Tracing and AI Performance; Specifications Leak

Dimensity 9500 SoC is rumoured to be in growth as the newest flagship-tier smartphone processor from MediaTek. Ahead of its anticipated debut someday later this yr, a tipster means that it might be fabricated utilizing TSMC’s N3P course of (3nm). Powered by Arm’s newest Cortex-X9 sequence cores, the chipset is speculated to deliver enhancements associated to ray tracing and synthetic intelligence (AI) — the latter supported by a neural processing unit (NPU) able to delivering 100 tera operations per second (TOPS) efficiency.

Tipster Digital Chat Station (translated from Chinese) leaked specs of the purported MediaTek Dimensity 9500 chipset in a put up on the Chinese microblogging platform Weibo. Fabricated utilizing the N3P course of, the SoC is tipped to include an octa-core structure, although its make-up might be completely different in contrast to what earlier rumours urged.

Instead of getting a 2 + 6 configuration, the Dimensity 9500 chipset might have one Cortex-X930 prime cores dubbed “Travis”, three cores dubbed “Alto”, and 4 Cortex-A730 “Gelas” cores.

The SoC is alleged to be complemented by an Immortalis-Drage GPU which might provide enhancements by way of ray tracing and AI, whereas additionally lowering the ability consumption, courtesy of a brand new GPU microarchitecture. Meanwhile, an NPU 9.0 is tipped to ship 100 TOPS of AI efficiency. As per the tipster, the Dimensity 9500 chipset may have 16MB of L3 cache and 10MB of SLC cache. Touted to be a flagship providing, it could help gadgets geared up with up to LPDDR5X RAM and up to UFS 4.1 storage.

Past stories counsel that the N3P course of utilized by TSMC for the purported chipset’s fabrication might end in a 5 p.c efficiency acquire and a 5-10 p.c effectivity enchancment as in contrast to the present Dimensity 9400 SoC which is constructed utilizing the N3E course of. It can also profit from improved multi-thread efficiency with the usage of Arm’s Scalable Matrix Extension (SME) which might speed up AI and ML-based functions and present enhanced help for matrix operations.

Although no official particulars are identified relating to the launch timeline of the Dimensity 9500 SoC, its predecessor was introduced in October 2024, and the purported chip might additionally launch across the identical time this yr.